GPU Architecture Basics
PremiumUnderstand GPU design philosophy, the SIMT model, and hardware hierarchy mapping to build parallel intuition.
Get code accessUnderstand GPU design philosophy, the SIMT model, and hardware hierarchy mapping to build parallel intuition.
Get code accessBefore writing any CUDA code, we need to switch our mental model.
CPU and GPU are built for computation, but they solve very different physical problems. Think Ferrari vs bus:

A GPU is not a standalone compute platform; it is a coprocessor for the CPU.
When we say “GPU parallel computing,” we really mean a CPU + GPU heterogeneous architecture:
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Bottleneck alert: PCIe bandwidth (tens of GB/s) is far below GPU VRAM bandwidth (TB/s). Frequent host-device transfers are the biggest performance killer. First rule of fast kernels: keep data on the GPU.
Intuition: If you need to move 100 bricks from A to B:
On the chip, CPU area is mostly Control and Cache; GPU area is mostly ALUs. This drives their division of labor:
| Feature | CPU | GPU |
|---|---|---|
| Core count | Few (dozens) | Many (thousands) |
| Best at | Control-heavy (branching, logic) | Compute-heavy (data-parallel) |
| Threads | Heavyweight (expensive context switches) | Lightweight (fast switching to hide latency) |
That means: GPUs are bad at complex control flow, but excellent at repeating the same compute over large data.
Thus CPU+GPU is complementary:
Why do GPUs dominate AI today? Not just because they have more cores.
As Moore’s Law hits physical limits, single-core performance gains slow down. Hennessy & Patterson argue that future gains will come from domain-specific architectures.
GPU is the early example: if you cannot make one worker faster (latency limit), hire ten thousand workers (throughput win).
In 2007, NVIDIA released CUDA, enabling GPU programming in C-like code instead of graphics APIs. This began the GPGPU era.
Modern NVIDIA GPUs (Volta and later) add Tensor Cores alongside standard CUDA cores.
That is why LLM training and inference always emphasize “maxing out Tensor Cores.”